industrial temperature range idt74fct2574at/ct fast cmos octal d register (3-state) 1 january 2004 industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. ? 2004 integrated device technology, inc. dsc-5495/3 features: ? a and c grades ? low input and output leakage 1a (max.) ? cmos power levels ? true ttl input and output compatibility: ?v oh = 3.3v (typ.) ?v ol = 0.3v (typ.) ? resistor outputs (-15ma i oh , 12ma i ol ) ? meets or exceeds jedec standard 18 specifications ? reduced system switching noise ? available in soic and qsop packages functional block diagram idt74fct2574at/ct fast cmos octal d register (3-state) description: the fct2574t is an 8-bit register built using an advanced dual metal cmos technology. these registers consist of eight d-type flip-flops with a buffered common clock and buffered 3-state output control. when the output enable ( oe ) input is low, the eight outputs are enabled. when the oe input is high, the outputs are in the high-impedance state. input data meeting the set-up and hold time requirements of the d inputs is transferred to the q outputs on the low-to-high transition of the clock input. the fct2574t has balanced output drive with current limiting resistors. this offers low ground bounce, minimal undershoot and controlled output fall times-reducing the need for external series terminating resistors. fct2574t parts are plug-in replacements for fct574t parts. d 0 q 0 d 1 q 1 d 2 q 2 d 3 q 3 d 4 q 4 d 5 q 5 d 6 q 6 d 7 q 7 cp oe d q cp d cp d cp d cp d cp d cp d cp d cp qqq q q qq
industrial temperature range 2 idt74fct2574at/ct fast cmos octal d register (3-state) pin configuration symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +7 v v term (3) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?60 to +120 ma absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. no terminal voltage may exceed vcc by +0.5v unless otherwise noted. 2. inputs and vcc terminals only. 3. output and i/o terminals only. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 6 10 pf c out output capacitance v out = 0v 8 12 pf capacitance (t a = +25c, f = 1.0mhz) note: 1. this parameter is measured at characterization but not tested. soic/ qsop top view 2 3 1 16 15 14 11 19 18 20 17 13 12 v cc q 0 q 3 q 1 q 2 q 4 q 7 q 5 q 6 cp 5 6 7 4 8 9 10 oe d 0 d 1 d 3 d 4 d 5 d 7 gnd d 2 d 6 pin names description dx d flip-flop data inputs c p clock pulse for the register. enters data on low-to- high transition. q x 3-state outputs (true) q x 3-state outputs (inverted) oe active low 3-state output enable input pin description note: 1. h = high voltage level x = don?t care l = low voltage level z = high impedance nc = no change = low-to-high transition function table (1) inputs outputs internal function oe cp dx qx q x high-z h l x z n c hhxznc load l llh register l hh l h lzh h hzl
industrial temperature range idt74fct2574at/ct fast cmos octal d register (3-state) 3 symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2 ? ? v v il input low level guaranteed logic low level ? ? 0.8 v i ih input high current (4) v cc = max. v i = 2.7v ? ? 1a i il input low current (4) v cc = max. v i = 0.5v ? ? 1a i ozh high impedance output current v cc = max v o = 2.7v ? ? 1a i ozl (3-state output pins) (4) v o = 0.5v ? ? 1 i i input high current (4) v cc = max., v i = v cc (max.) ? ? 1a v ik clamp diode voltage v cc = min, i in = -18ma ? ?0.7 ?1.2 v v h input hysteresis ? ? 200 ? mv i cc quiescent power supply current v cc = max., v in = gnd or v cc ? 0.01 1 ma dc electrical characteristics over operating range following conditions apply unless otherwise specified: industrial: t a = ?40c to +85c, v cc = 5.0v 5% notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. not more than one output should be tested at one time. duration of the test should not exceed one second. 4. the test limit for this parameter is 5a at t a = ?55c. symbol parameter test conditions (1) min. typ. (2) max. unit i odl output low current v cc = 5v, v in = v ih or v il , v out = 1.5v (3) 16 48 ? m a i odh output high current v cc = 5v, v in = v ih or v il , v out = 1.5v (3) ?16 ?48 ? ma v oh output high voltage v cc = min i oh = ?15ma 2.4 3.3 ? v v in = v ih or v il v ol output low voltage v cc = min i ol = 12ma ? 0.3 0.5 v v in = v ih or v il output drive characteristics
industrial temperature range 4 idt74fct2574at/ct fast cmos octal d register (3-state) symbol parameter test conditions (1) min. typ. (2) max. unit ? i cc quiescent power supply current v cc = max. ? 0.5 2 ma ttl inputs high v in = 3.4v (3) i ccd dynamic power supply v cc = max. v in = v cc ? 0.06 0.12 ma/ current (4) outputs open v in = gnd mhz oe = gnd one input toggling 50% duty cycle i c total power supply current (6) v cc = max. v in = v cc ? 0.6 2.2 ma outputs open v in = gnd f cp = 10mhz 50% duty cycle oe = gnd v in = 3.4v ? 1.1 4.2 fi = 5mhz v in = gnd one bit toggling 50% duty cycle v cc = max. v in = v cc ? 1.5 4 (5) outputs open v in = gnd f cp = 10mhz 50% duty cycle oe = gnd v in = 3.4v ? 3.8 13 (5) eight bits toggling v in = gnd fi = 2.5mhz 50% duty cycle notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. per ttl driven input; (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of ? i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + ? i cc d h n t + i ccd (f cp /2+ f i n i ) i cc = quiescent current ? i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = output frequency n i = number of outputs at f i all currents are in milliamps and all frequencies are in megahertz. power supply characteristics
industrial temperature range idt74fct2574at/ct fast cmos octal d register (3-state) 5 notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not tested. fct2574at fct2574ct symbol parameter condition (1) min. (2) max. min. (2) max. unit t plh propagation delay c l = 50pf 2 6.5 2 5.2 ns t phl cp to qx r l = 500 ? t pzh output enable time 1.5 6.5 1.5 5.5 ns t pzl t phz output disable time 1.5 5.5 1.5 5 ns t plz t su set-up time, high or low 2 ? 2 ? ns dx to cp t h hold time, high or low 1.5 ? 1.5 ? ns dx to cp t w cp pulse width high or low (3) 5?5?ns switching characteristics over operating range
industrial temperature range 6 idt74fct2574at/ct fast cmos octal d register (3-state) pulse generator r t d.u.t . v cc v in c l v out 50pf 500 ? 500 ? 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. octal link octal link octal link octal link octal link test circuits and waveforms propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times pulse width notes: 1. diagram shown for input control enable-low and input control disable-high. 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns. test switch open drain disable low closed enable low all other tests open switch position definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator.
industrial temperature range idt74fct2574at/ct fast cmos octal d register (3-state) 7 ordering information idt xx temp. range xxxx device type x package fct so q 2574at 2574ct small outline ic quarter-size small outline package fast cmos octal d register (3-state) 74 - 40c to +85c corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com
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